List of Publications

Dr. Bruce F. Cockburn
Department of Electrical and Computer Engineering
University of Alberta
9107 - 116 St. NW, ECERF Building, 2nd floor
Edmonton, AB T6G 2V4
Canada

Journal Articles

  1. Amirhossein Alimohammad and Bruce Cockburn, “A Unified Architecture for the Accurate and High-Throughput Implementation of Six Key Elementary Functions on Reconfigurable Hardware,” submitted on Dec. 22, 2008 to IEEE Transactions on Computers, accepted August 19, 2009, 8 pp.
  2. Zhengang Chen, Tyler Brandon, Duncan G. Elliott, Stephen Bates, Witold Kryzmien and Bruce F. Cockburn, “Jointly Designed Architecture-Aware LDPC Convolutional Codes and High-Throughput Parallel Encoders/Decoders,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 57, no. 4, April 2010, 14 pp.
  3. Amirhossein Alimohammad, Saeed Fouladi Fard and Bruce Cockburn, “An Improved Layered MIMO Detection Algorithm With Near-Optimal Performance,” IET Electronics Letters, vol. 45, no. 13, June 18, 2009, pp. 675-677.
  4. Tyler Brandon, John C. Koob, Leendert van den Berg, Zhengang Chen, Amirhossein Alimohammad, Ramkrishna Swamy, Jason Klaus, Stephen Bates, Vincent C. Gaudet, Bruce F. Cockburn and Duncan G. Elliott, “A Compact 1.1-Gb/s Encoder and a Memory-Based 600-Mb/s Decoder for LDPC Convolutional Codes,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 5, May 2009, pp. 1017-1029.
  5. Amirhossein Alimohammad, Saeed Fouladi Fard and Bruce F. Cockburn, “Compact Rayleigh and Rician Fading Simulator Based on Random Walk Processes,” IET Communications, vol. 3, no. 8, Aug. 2009, pp. 1333-1342.
  6. Zhengang Chen, Tyler L. Brandon, Stephen Bates, Duncan G. Elliott and Bruce F. Cockburn, “Efficient Implementation of Low-Density Parity-Check Convolutional Code Encoders with Built-In Termination,” IEEE Transactions on Circuits and Systems Part I: Regular Papers, vol. 55, no. 11, Dec. 2008, pp. 3628-3640.
  7. Amirhossein Alimohammad and Bruce F. Cockburn, “Modeling and Hardware Implementation Aspects of Fading Channel Simulators,” IEEE Transactions on Vehicular Technology, vol. 57, no. 4, July 2008, pp. 2055-2069.
  8. Tyler L. Brandon, Robert Hang, Gary Block, Vincent Gaudet, Bruce F. Cockburn, Sheryl L. Howard, Christian Giasson, Keith Boyle, Siavash Sheik Zeinoddin, Anthony Rapley, Stephen Bates, Duncan G. Elliott, and Christian Schlegel, “A Scalable LDPC Decoder ASIC Architecture with Bit-Serial Message Exchange,” Integration, the VLSI Journal, vol. 41, no. 3, May 2008, pp. 385-398.
  9. Amirhossein Alimohammad, Saeed Fouladi Fard, Bruce F. Cockburn and Christian Schlegel, “A Compact Single-FPGA Fading Channel Simulator,” submitted on Nov. 3, 2006 and accepted on August 20, 2007 for publication in IEEE Transactions on Circuits and Systems Part II: Express Briefs, vol. 55, no. 1, Jan. 2008, pp. 84-88.
  10. Amirhossein Alimohammad, Saeed Fouladi Fard, Bruce F. Cockburn, and Christian Schlegel, “A Compact and Accurate Gaussian Variate Generator,” submitted on Sept. 18, 2006 to IEEE Transactions on Very Large Scale Integration Systems, vol. 16, no. 5, May 2008, pp. 517-527.
  11. Ramkrishna Swamy, Stephen Bates, Tyler L. Brandon, Bruce F. Cockburn, Duncan G. Elliott, John Koob, and Zhengang Chen, “Design and Test of a 180-nm CMOS, Rate-1/2 (128,3,6) Low-Density Parity-Check Convolutional Code Encoder and Decoder System,” IEEE Journal of Solid-State Circuits, vol. 42, no. 10, Oct. 2007, pp. 2245-2256.
  12. Yufei Yuan, Bruce F. Cockburn, Thomas Sikora and Mrinal Mandal, “A GOP Based Packetization Technique for Video Streaming,” Journal of Electronic Imaging, vol. 16, article 023012 (May 15, 2007), 12 pp.
  13. Tyler L. Brandon, Duncan G. Elliott, and Bruce F. Cockburn, “Using Stacked Bitlines and Hybrid ROM Cells to Form ROM and SRAM-ROM with Increased Storage Density,” IEEE Transactions on Circuits and Systems, Part I Regular Papers, vol. 53, no. 12, Dec. 2006, pp. 2595-2605.
  14. Amirhossein Alimohammad and Bruce F. Cockburn, “An Efficient Parallel Architecture for Implementing LST Decoding in MIMO Systems,” IEEE Transactions on Signal Processing, vol. 54, no. 10, Oct. 2006, pp. 3899-3907.
  15. John C. Koob, Raymond J. Sung, Tyler L. Brandon, Daniel A. Leder, Duncan G. Elliott, Bruce F. Cockburn, and Lisa McIlrath, “Design of a 3D Fully-Depleted SOI Computational RAM,” IEEE Transactions on Very Large Scale Integration Systems, vol. 13, no. 3, March 2005, pp. 358-369.
  16. Hongyu Liao, Mrinal Kr. Mandal, and Bruce F. Cockburn, “Efficient Architectures for 1-D and 2-D Lifting-Based Wavelet Transforms,” IEEE Transactions on Signal Processing, vol. 52, no. 5, May 2004, pp. 1315-1326.
  17. Hongyu Liao, Mrinal Kr. Mandal, and Bruce F. Cockburn, “Efficient Implementation of the Lifting-based Discrete Wavelet Transform,” IEE Electronics Letters, vol. 38, no. 18, Aug. 29, 2002, pp. 1010-1012.
  18. Yunan Xiang, Bruce F. Cockburn, and Duncan G. Elliott, “Design of a Multilevel DRAM with Adjustable Cell Capacity,” Canadian Journal of Electrical and Computer Engineering, vol. 26, no. 2, Apr. 2001, pp. 55-59.
  19. Jeremy S. Sewall and Bruce F. Cockburn, “Voiceband Signal Classification Using Statistically Optimal Combinations of Low-Complexity Discriminant Variables,” IEEE Transactions on Communications, vol. 47, no. 11, Nov. 1999, pp. 1622-1627.
  20. Michael Redeker, Bruce F. Cockburn, and Duncan G. Elliott, “Fault Models and Tests for a 2-Bit-per-Cell MLDRAM,” IEEE Design & Test of Computers, vol. 16, no. 1, Jan.-Mar., 1999, pp. 22-31.
  21. Bruce F. Cockburn, Fabrizio Lombardi, and Fred J. Meyer, “Guest Editors' Introduction: DRAM Architecture and Testing,” IEEE Design & Test of Computers, vol. 16, no. 1, Jan.-Mar., 1999, pp. 19-21.
  22. Bruce F. Cockburn, “Tutorial on Semiconductor Memory Testing,” included in the Special Issue on Testing of Multi-Megabit Memories of JETTA - Journal of Electronic Testing: Theory and Applications, v. 5, no. 4, Nov. 1994, pp. 321-336.
  23. Bruce F. Cockburn, “Deterministic Tests for Detecting Single V-Coupling Faults in RAMs,” JETTA - Journal of Electronic Testing: Theory and Applications, v. 5, no. 1, Feb. 1994, pp. 91-113.
  24. Bruce F. Cockburn and J. A. Brzozowski, “Near-Optimal Tests for Classes of Write-Triggered Coupling Faults in RAMs,” JETTA - Journal of Electronic Testing: Theory and Applications, v. 3, no. 3, Aug. 1992, pp. 251-264.
  25. Janusz A. Brzozowski and Bruce F. Cockburn, “Detection of Coupling Faults in RAMs,” JETTA - Journal of Electronic Testing: Theory and Applications, v. 1, no. 2, May 1990, pp. 151-162.
  26. Bruce F. Cockburn and Janusz A. Brzozowski, “Switch-Level Testability of the Dynamic CMOS PLA,” Integration: the VLSI Journal, v. 9, no. 1, Feb. 1990, pp. 49-80.

Journal Articles in Preparation or in Review

  1. Amirhossein Alimohammad, Saeed Fouladi Fard and Bruce F. Cockburn, “A Compact Hardware Simulator for Nakagami-m and Weibull Fading Channels,” submitted on Sept. 18, 2009 to IEEE Transactions on Vehicular Technology.
  2. Saeed Fouladi Fard, Amirhossein Alimohammad and Bruce F. Cockburn, “Complex IIR-Filter Design for Compact and Stable Fixed-Point Implementation,” submitted on Sept. 14, 2009 to IEEE Trans. on Circuits and Systems Part II: Express Briefs, 9 pp.
  3. Amirhossein Alimohammad, Saeed Fouladi Fard and Bruce F. Cockburn, “Simulation of Multipath MIMO Channels Using a Compact and High-Throughput Reconfigurable Architecture,” submitted on Sept. 11, 2009 to IET Communications.
  4. Saeed Fouladi Fard, Amirhossein Alimohammad and Bruce F. Cockburn, “A Single FPGA Simulator for Geometric MIMO Fading Channel Models,” submitted on Sept. 11, 2009 to IET Communications.
  5. Saeed Fouladi Fard, Amirhossein Alimohammad and Bruce F. Cockburn, “Accurate Simulation of Nonisotropic Fading Channels with Arbitrary Temporal Correlation,” submitted on Sept. 11, 2009 to IET Signal Processing.
  6. Saeed Fouladi Fard, Amirhossein Alimohammad and Bruce F. Cockburn, “An FPGA-Based Simulator for High Path Count Rayleigh and Rician Fading,” submitted on Sept. 11, 2009 to IEEE Transactions on Vehicular Technology.
  7. John Koob, Tyler Brandon, Leendert van den Berg, Zhengang Chen, Amirhossein Alimohammad, Ramkrishna Swamy, Jason Klaus, Stephen Bates, Vincent Gaudet, Bruce Cockburn and Duncan Elliott, “A Compact 1.1-Gb/s Encoder and a Memory-Based 600-Mb/s Decoder for LDPC Convolutional Codes,” submitted on Feb. 13, 2009 to IEEE Transactions on Circuits and Systems I: Regular Papers, 13 pp.
  8. Amirhossein Alimohammad, Saeed Fouladi Fard and Bruce Cockburn, “An Iterative Detector for MIMO Systems,” submitted on Feb. 9, 2009 to IEEE Transactions on Wireless Communications, 9 pp.
  9. Amirhossein Alimohammad, Saeed Fouladi Fard and Bruce Cockburn, “Accurate Simulation of Wireless Radio Propagation Using a Compact and High-Throughput Reconfigurable Architecture,” submitted on Feb. 5, 2009 to IEEE Transactions on Communications, 18 pp.
  10. Amirhossein Alimohammad, Saeed Fouladi Fard, Bruce F. Cockburn and Christian Schlegel, “A Compact and High-Throughput Architecture for Simulating Wireless Radio Propagation,” submitted on June 6, 2008 to IEEE Communication Letters.
  11. Saeed Fouladi Fard, Amirhossein Alimohammad, Bruce F. Cockburn and Christian Schlegel, “Efficient Hardware Simulation of Nonisotropic Fading with Arbitrary Temporal Correlation,” submitted on May 2, 2008 to IEEE Transactions on Signal Processing.
  12. Amirhossein Alimohammad, Saeed Fouladi Fard and Bruce F. Cockburn, “Accurate Simulation of Multipath MIMO Channels Using An Improved Sum-of-Sinusoids Based Fading Channel Model,” submitted on Nov. 30, 2007 to IEEE Transactions on Signal Processing, in revision.
  13. Amirhossein Alimohammad, Saeed Fouladi Fard, Bruce F. Cockburn and Christian Schlegel, “Enhanced Nonlinear and Combined Linear-Nonlinear Pseudo-Random Number Generators for Hardware-Based Simulations and Testing,” submitted on Nov. 30, 2007 to IEEE Transactions on Computers.

Patents and Patent Applications

  1. Amirhossein Alimohammad, Saeed Fouladi Fard, Bruce F. Cockburn and Christian Schlegel, “Signal Filtering and Filter Design Techniques,” US Provisional Patent Application no. 60/888,630 filed February 7, 2007, and PCT patent application no. PCT/US2008/001601 filed February 7, 2008.
  2. Stephen Bates, Christian Schlegel, Bruce F. Cockburn, and Vincent Gaudet, “Decoder for Low-Density Parity-Check Convolutional Codes,” PCT application filed on Dec. 14, 2005.
  3. Stephen Bates, Christian Schlegel, Vincent Gaudet, and Bruce F. Cockburn, “Memory Architectures for Low-Density Parity-Check Convolutional Code Decoders,” U.S. pat. applic. no. 60/682,178 filed May 18, 2005.
  4. Vincent Gaudet, Bruce F. Cockburn, Christian Schlegel, Stephen Bates, Paul Goud, Robert Hang, Anthony Rapley, and Sheryl Howard, “Bit-serial Method and Apparatus for Decoding Low Density Parity Check Codes,” provisional U.S. pat. applic. no. 60/570,901 filed May 14, 2004. Full PCT patent application no. PCT/CA2005/000731, titled “Method and Apparatus for Digit-Serial Communications for Iterative Digital Processing Algorithms,” filed on May 13, 2005. The PCT application was nationalized in the US as application no. 11/569,017 filed on November 13, 2006.
  5. Hongyu Liao, Mrinal K. Mandal, and Bruce F. Cockburn, “Implementation of Discrete Wavelet Transform Using Lifting Steps,” U.S. Pat. No. 7,480,416, issued Jan. 20, 2009. Also filed as a Canadian patent application CA 2428393 on May 9, 2003.
  6. Gershom Birk, Duncan G. Elliott, and Bruce F. Cockburn, “Multilevel DRAM,” U.S. Patent Application No. 20020053007 filed May 2, 2002.
  7. Gershom Birk, Duncan Elliott and Bruce F. Cockburn, “System and Method for Multilevel DRAM Sensing and Restoring,” U.S. Pat. No. 6,556,469 filed January 24, 2001 and issued April 29, 2003.
  8. Gershom Birk, Duncan G. Elliott, and Bruce F. Cockburn, “Improved Multilevel DRAM,” Canadian Pat. Applic. 2,373,460 filed May 26, 2000. Simultaneously submitted as Japanese patent 2001-500279, Korean patent 2001-7015148, and PCT patent PCT/CA00/00613.
  9. Bruce F. Cockburn, Duncan G. Elliott and Gershom Birk, “Multilevel DRAM with Local Reference Generation,” Canadian Pat. Applic. 2,273,122 filed May 26, 1999. Abandoned May 27, 2002.
  10. Jeremy S. Sewall, Deepak P. Sarda and Bruce F. Cockburn, “Voiceband Signal Classifier,” Canadian Pat. CA 2,271,494, filed May 11, 1999 and allowed Feb. 17, 2004.
  11. Jeremy S. Sewall, Deepak P. Sarda and Bruce F. Cockburn, “Voiceband Signal Classifier,” U.S. Pat. 6,708,146 B1, filed April 30, 1999 and issued Mar 16, 2004.
  12. Jeremy S. Sewall and Bruce F. Cockburn, “Voiceband Signal Classifier,” Canadian Pat. CA 2,194,332, filed Jan. 3, 1997 and issued Aug. 13, 2002.
  13. Bruce F. Cockburn, “Method and Apparatus for Testing Electronic Memories for the Presence of Multiple Cell Coupling Faults,” U.S. Pat. No. 5,506,959 filed Aug. 4, 1994 and issued April 9, 1996. Also, Canadian Pat. CA 2,129,390 filed Aug. 3, 1994 and issued Apr. 14, 1998.

Conference Papers

  1. Saeed Fouladi Fard, Amirhossein Alimohammad and Bruce F. Cockburn, “A Flexible FPGA-Based MIMO Geometric Fading Channel Simulator for Rapid Prototyping,” 2009 International Conference on Field-Programmable Technology (FPT'09), Dec. 9-11, 2009, Sydney, Australia, 4 pp.
  2. Saeed Fouladi Fard, Amirhossein Alimohammad, Bruce F. Cockburn, and Christian Schlegel, “A Versatile Fading Simulator for On-Chip Verification of MIMO Communication Systems,” accepted June 12, 2009 for presentation at the 22nd IEEE International System-on-Chip Conference (SOCC 2009), Sept. 9-11, 2009, Belfast, Northern Ireland, U.K., 4 pp.
  3. Saeed Fouladi Fard, Amirhossein Alimohammad, Bruce F. Cockburn, and Christian Schlegel, “High Path-Count Multirate Rayleigh Fading Channel Simulator with Time-Multiplexed Datapath,” accepted June 12, 2009 for presentation at the 22nd IEEE International System-on-Chip Conference (SOCC 2009), Sept. 9-11, 2009, Belfast, Northern Ireland, U.K., 4 pp.
  4. Amirhossein Alimohammad, Saeed Fouladi Fard and Bruce F. Cockburn, “FPGA-Accelerated Baseband Design and Verification of Broadband MIMO Wireless Systems,” accepted June 1 for presentation at the First International Conference on Advances in System Testing and Validation Lifecycle (VALID 2009), Sept. 20-25, 2009, Porto, Portugal, pp. 135-140. Received one of the seven Best Paper Awards.
  5. Saeed Fouladi Fard, Amirhossein Alimohammad, Bruce F. Cockburn, and Christian Schlegel, “A Single FPGA Filter-Based Multipath Fading Emulator,” accepted for presentation at IEEE Globecom 2009, Nov. 30 to Dec. 4, Honolulu, HI, U.S.A., 6 pp.
  6. Amirhossein Alimohammad, Saeed Fouladi Fard and Bruce F. Cockburn, “FPGA-based Accelerator for the Verification of Leading-Edge Wireless Systems,” accepted for presentation at the 46th Design Automation Conference (DAC 2009), July 26-31, 2009, San Francisco, CA, pp. 844-847.
  7. Amirhossein Alimohammad, Saeed Fouladi Fard and Bruce F. Cockburn, “A Flexible Layered Architecture for Accurate Digital Baseband Algorithm Development and Verification,” 2009 Design, Automation & Test in Europe Conference (DATE 2009), Apr. 20-24, 2009, Nice, France, pp. 45-50.
  8. Amirhossein Alimohammad, Saeed Fouladi Fard and Bruce F. Cockburn, “Hardware-based Error Rate Testing of Digital Baseband Communication Systems,” 2008 IEEE International Test Conference (ITC 2008), Oct. 26-31, 2008, Santa Clara, CA, U.S.A., Paper L4.3, 8 pp.
  9. Amirhossein Alimohammad, Saeed Fouladi Fard, Bruce F. Cockburn and Christian Schlegel, “A Novel Technique for Efficient Hardware Simulation of Spatiotemporally Correlated MIMO Fading Channels,” 2008 IEEE International Conference on Communications (ICC 2008), May 19-23, 2008, Beijing, P.R. China, Paper SP1-1., pp. 718-724.
  10. John Koob, Tyler Brandon, Leendert van den Berg, Zhengang Chen, Amirhossein Alimohammad, Ramkrishna Swamy, Jason Klaus, Stephen Bates, Vincent Gaudet, Bruce Cockburn and Duncan Elliott, “A 600-Mb/S Encoder and Decoder for Low-Density Parity-Check Convolutional Codes,” 2008 IEEE International Symposium on Circuits and Systems (ISCAS 2008), May 18-21, 2008, Seattle, WA, U.S.A., pp. 3090-3093.
  11. Amirhossein Alimohammad, Saeed Fouladi Fard, Bruce F. Cockburn and Christian Schlegel, “A Single-FPGA Multipath MIMO Fading Channel Simulator,” 2008 IEEE International Symposium on Circuits and Systems (ISCAS 2008), May 18-21, 2008, Seattle, WA, U.S.A., pp. 308-311.
  12. Amirhossein Alimohammad, Saeed Fouladi Fard, Bruce F. Cockburn and Christian Schlegel, “An Accurate and Compact Rayleigh and Rician Fading Channel Simulator,” 2008 IEEE 67th Vehicular Technology Conference (VTC2008-Spring), May 11-14, 2008, Marina Bay, Singapore., pp. 409-413.
  13. Amirhossein Alimohammad, Saeed Fouladi Fard, Bruce F. Cockburn and Christian Schlegel, “On the Efficiency and Accuracy of Hybrid Pseudo-Random Number Generators for FPGA-Based Simulations,” 2008 IEEE 15th Reconfigurable Architectures Workshop (RAW 2008), Apr. 14-15, 2008, Miami, FL, U.S.A.
  14. Xin Sheng Zhou, Bruce F. Cockburn and Stephen Bates, “Improved Iterative Bit Flipping Decoding Algorithms for LDPC Convolutional Codes,” 2007 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM'07), Victoria, BC, Canada, August 22-24, 2007, pp. 541-544.
  15. Amirhossein Alimohammad, Saeed Fouladi Fard, Bruce F. Cockburn and Christian Schlegel, “An Improved SOS-based Fading Channel Emulator,” 2007 IEEE 66th Vehicular Technology Conference (VTC2007-Fall), Sept. 30 - Oct. 3, 2007, Baltimore, MD, U.S.A., pp. 931-935.
  16. Amirhossein Alimohammad, Saeed Fouladi Fard, Bruce F. Cockburn and Christian Schlegel, “A Compact Fading Channel Simulator Using Timing-Driven Resource Sharing,” 18th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP'07), July 8-11, 2007, Montreal, QC, Canada.
  17. Amirhossein Alimohammad, Saeed Fouladi Fard, Bruce F. Cockburn and Christian Schlegel, “A Flexible Filter Processor for Fading Channel Simulation,” 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2007), Apr. 14-15, 2007, Napa, CA, U.S.A., pp. 339-342.
  18. Saeed Fouladi Fard, Amirhossein Alimohammad, Mazia Khorasani, Bruce F. Cockburn and Christian Schlegel, “A Compact and Accurate FPGA based Nonisotropic Fading Channel Simulator,” 2007 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE'07), Apr. 22-25, 2007, Vancouver, BC, Canada, paper 69.2, pp. 1239-1242.
  19. Xin Sheng Zhou, Bruce F. Cockburn and Stephen Bates, “Quantitive Evaluation of Low Density Parity Check Convolutional Code Encoder and Decoder Algorithms for the XInC MIMD Multithreaded Microprocessor,” 2007 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE'07), Apr. 22-25, 2007, Vancouver, BC, Canada, paper 76.1, pp. 1361-1365.
  20. Saeed Sharifi Tehrani, Bruce F. Cockburn and Stephen Bates, “On the Effects of Colored Noise on the Performance of LDPC Codes,” presented at the IEEE 2006 International Workshop on Signal Processing Systems (SIPS 2006), Oct. 2-4, 2006, Banff, AB, Canada.
  21. Amirhossein Alimohammad and Bruce F. Cockburn, “A Reconfigurable SOS-based Rayleigh Fading Channel Simulator,” presented at the IEEE 2006 International Workshop on Signal Processing Systems (SIPS 2006), Oct. 2-4, 2006, Banff, AB, Canada.
  22. Amirhossein Alimohammad and Bruce F. Cockburn, “Compact Implementation of a Sum-of-Sinusoids Rayleigh Fading Channel Simulator,” accepted for presentation at the 6th IEEE International Symposium on Signal Processing and Information Technology (ISSPIT 2006), Aug. 27-30, 2006, Vancouver, BC, Canada, pp. 253-257.
  23. Bruce F. Cockburn and Keith Boyle, “Design and Characterization of a Digital Delay Locked Loop Synthesized from Black Box Standard Cells,” 2006 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE-06), May 7-10, 2006, Ottawa, ON, Canada, pp. 926-929.
  24. J. Koob, D. G. Elliott and B. F. Cockburn, “An Empirical Evaluation of Semiconductor File Memory as a Disk Cache,” 4th IEEE Workshop on Memory Performance Issues (WMPI-2006), Austin, TX, USA, Feb. 11, 2006, held in conjunction with the 12th International Symposium on High-Performance Computer Architecture (HPCA-12), pp. 93-100.
  25. Saeed Sharifi Tehrani, Bruce F. Cockburn and Stephen Bates, “Performance Evaluation of LDPC Codes in the Presence of Colored Noise,” 2005 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, Victoria, BC, Canada, August 24-26, 2005, pp. 81-84.
  26. Amirhossein Alimohammad, Bruce F. Cockburn and Christian Schlegel, “An Iterative Hardware Gaussian Noise Generator,” 2005 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, Victoria, BC, Canada, August 24-26, 2005, pp. 649-652.
  27. Kamlesh R. Raiter and Bruce F. Cockburn, “An Investigation into a Three-level Ferroelectric Memory,” 2005 IEEE International Workshop on Memory Technology, Design and Testing, Taipei, Taiwan, Aug. 3-5, 2005, pp. 38-43.
  28. Kamlesh R. Raiter and Bruce F. Cockburn, “Auto-calibration Technique for On-chip Reference Voltage Generation in Ferroelectric Memories,” 2005 IEEE Canadian Conference on Electrical and Computer Engineering, Saskatoon, SK, Canada, May 1-4, 2005, pp. 684-687.
  29. Saeed Sharifi Tehrani, Bruce F. Cockburn and Stephen Bates, “Performance Evaluation of LDPC Codes in the Presence of ISI with Application to 10GBASE-T Ethernet,” 2005 IEEE Canadian Conference on Electrical and Computer Engineering, Saskatoon, SK, Canada, May 1-4, 2005, pp. 2079-2082.
  30. Amirhossein Alimohammad, Bruce F. Cockburn and Christian Schlegel, “Area-efficient Parallel White Gaussian Noise Generator,” 2005 IEEE Canadian Conference on Electrical and Computer Engineering, Saskatoon, SK, Canada, May 1-4, 2005, pp. 1855-1858.
  31. Tyler Brandon, Duncan G. Elliott and Bruce F. Cockburn, “HDL2GDS: A Fully Automated ASIC Digital Design Flow,” 2005 IEEE Canadian Conference on Electrical and Computer Engineering, Saskatoon, SK, Canada, May 1-4, 2005, pp. 1477-1480.
  32. Jesus Hernandez Tapia, Duncan Elliott and Bruce F. Cockburn, “Measuring the Potential Benefits of a Dynamically Adaptive Cache Line Size,” 2005 IEEE Canadian Conference on Electrical and Computer Engineering, Saskatoon, SK, Canada, May 1-4, 2005, pp. 1938-1941.
  33. John Koob, Sue-Ann Ung, Ashwin S. Rao, Daniel A. Leder, Tyler L. Brandon, Craig S. Joly, Mike Hume, Michael Redeker, Bruce F. Cockburn and Duncan G. Elliott, “Test and Characterization of a Variable-Capacity Multilevel DRAM,” 2005 IEEE VLSI Test Symposium, Palm Springs, CA, U.S.A., May 1-5, pp. 189-197.
  34. B. F. Cockburn, “Tutorial on Magnetic Tunnel Junction Magnetoresistive Random-Access Memory,” 2004 IEEE International Workshop on Memory Technology, Design and Testing, San Jose, U.S.A., Aug. 9-10, pp. 46-51.
  35. Fang Pang, Tyler Brandon, B. F. Cockburn and Mike Hume, “A Reconfigurable Digital IC Tester Implemented using the ARM Integrator Rapid Prototyping System,” 2004 IEEE Canadian Conference on Electrical and Computer Engineering, Niagara Falls, ON, Canada, May 2-5, 2004, vol. 4, pp. 1931-5.
  36. Haiying "Helen" Qu and B. F. Cockburn, “Performance Evaluation of Three Memory Sense Amplifiers with Input Offset Cancellation,” 2004 IEEE Canadian Conference on Electrical and Computer Engineering, Niagara Falls, ON, Canada, May 2-5, 2004, vol. 4, pp. 1927-30.
  37. X. Sun, B. F. Cockburn, and D. G. Elliott, “An Efficient Functional Test for the Massively-Parallel C*RAM Logic-Enhanced Memory Architecture,” 2003 IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT'03), Cambridge, MA, USA, Nov 3-5, 2003, pp. 475-482.
  38. D. Salamon and B. F. Cockburn, “An Electrical Simulation Model for the Chalcogenide Phase-change Memory Cell,” 2003 IEEE International Workshop on Memory Technology, Design and Testing, San Jose, U.S.A., Jul. 28-29, 2003, pp. 86-91.
  39. B. F. Cockburn, J. Hernandez Tapia, and D. G. Elliott, “A Multilevel DRAM with Hierarchical Bitlines and Serial Sensing,” 2003 IEEE International Workshop on Memory Technology, Design and Testing, San Jose, U.S.A., Jul. 28-29, 2003, pp. 14-19.
  40. B. F. Cockburn, “The Emegence of High-density Semiconductor-compatible Spintronic Memory,” 2003 International Conference on MEMS, Nanotechnology, and Smart Systems, Banff, AB, Canada, July 20-23, 2003, pp. 321-326.
  41. John Koob, Raymond Sung, Tyler Brandon, Duncan G. Elliott, Bruce F. Cockburn, and Lisa McIlrath, “Design of a 3D Fully-Depleted SOI Computational RAM,” 28th European Solid-State Circuits Conference, ESSCIRC 2002, Florence, Italy, Sept. 24-26, 2002, paper C-149.
  42. Michael Redeker, Bruce F. Cockburn, Duncan G. Elliott, Yunan Xiang, and Sue Ann Ung, “Fault Modeling and Pattern-Sensitivity Testing for a Multilevel DRAM,” 2002 IEEE International Workshop on Memory Technology, Design and Testing, Isle de Bendor, France, Jul. 10-12, 2002, pp. 117-122.
  43. Michael Redeker, Bruce F. Cockburn, Duncan G. Elliott, “An Investigation into Crosstalk Noise in DRAM Structures,” 2002 IEEE International Workshop on Memory Technology, Design and Testing, Isle de Bendor, France, Jul. 10-12, 2002, pp. 123-129.
  44. B. F. Cockburn, “Survey of Emerging Nonvolatile Embedded Memory Technologies,” 2002 International Workshop on System-on-Chip for Real-Time Applications, Banff, AB, Canada, July 6-7, 2002, pp. 241-252.
  45. S. J. Dillen and B. F. Cockburn, “Parallel Filtering and Thresholding of Images on the SIMD DSP-RAM Architecture,” 2002 IEEE Canadian Conference on Electrical and Computer Engineering, Winnipeg, MB, Canada, May 12-15, 2002, pp. 995-1000.
  46. Hua Ai, N. Li, T. Li, Mrinal. Kr. Mandal, and B. F. Cockburn, “Efficient Implementation of Motion Estimation Technique on the Computational RAM Architecture,” 2002 IEEE Canadian Conference on Electrical and Computer Engineering, Winnipeg, MB, Canada, May 12-15, 2002, pp. 609-613.
  47. Hongyu Liao, Mrinal Kr. Mandal, and B. F. Cockburn, “Novel Architectures for the Lifting-Based Discrete Wavelet Transform,” 2002 IEEE Canadian Conference on Electrical and Computer Engineering, Winnipeg, MB, Canada, May 12-15, 2002, pp. 1020-1025.
  48. R. J. Sung, J. C. Koob, T. L. Brandon, D. G. Elliott, and B. F. Cockburn, “Design of an Embedded Fully-Depleted SOI SRAM,” 2001 IEEE International Workshop on Memory Technology, Design and Testing, San Jose, CA, U.S.A., Aug. 6-7, 2001, pp. 13-18.
  49. Y. Xiang, B. F. Cockburn, and D. G. Elliott, “Design of a Multilevel DRAM with Adjustable Cell Capacity,” 2001 IEEE Canadian Conference on Electrical and Computer Engineering, Toronto, ON, Canada, May 20-23, 2001, pp. 295-300.
  50. H.-Y. Liao, B. F. Cockburn, and Mrinal Kr. Mandal, “Efficient Implementation of the Discrete Wavelet Transform on the Parallel DSP-RAM Architecture,” 2001 IEEE Canadian Conference on Electrical and Computer Engineering, Toronto, ON, Canada, May 20-23, 2001, pp. 1189-1192.
  51. B. S.-H. Kwan, B. F. Cockburn, and D. G. Elliott, “Implementation of DSP-RAM: An Architecture for Parallel Digital Signal Processing,” 2001 IEEE Canadian Conference on Electrical and Computer Engineering, Toronto, ON, Canada, May 20-23, 2001, pp. 341-346.
  52. M. Kaya and B. F. Cockburn, “Experimental Evaluation of Voiceband Fractionally-Spaced Blind Equalizers Based on the Constant Modulus Algorithm,” 2000 IEEE Canadian Conference on Electrical and Computer Engineering, Halifax, NS, Canada, May 7-10, 2000, pp. 287-292.
  53. C. Wickman, D. G. Elliott, and B. F. Cockburn, “Cost Models for Large File Memory DRAMs with ECC and Bad Block Marking,” 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Albuquerque, NM, U.S.A., Nov. 1-3, 1999, pp. 319-327.
  54. Z. Wang, B. F. Cockburn, D. G. Elliott, and W. Krzymien, “DSP-RAM: A Logic-Enhanced Memory Architecture for Communication Signal Processing,” 1999 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, Victoria, BC, Canada, Aug. 22-24, 1999, pp. 475-478.
  55. G. Birk, D. G. Elliott, and B. F. Cockburn, “A Comparative Study of Four Multilevel DRAMs,” 1999 IEEE International Workshop on Memory Technology, Design and Testing, San Jose, CA, U.S.A., Aug. 9-10, 1999, pp. 102-109.
  56. X. Xu, B. F. Cockburn, and D. P. Sarda, “A DSP-less Real-Time Voiceband Signal Classifier Based on a Commodity Personal Computer Platform,” 1999 IEEE Canadian Conference on Electrical and Computer Engineering, Edmonton, AB, Canada, May 9-12, 1999, pp. 90-94.
  57. G. Birk, D. G. Elliott, and B. F. Cockburn, “Design and Characterization of an Embedded ASIC DRAM,” 1999 IEEE Canadian Conference on Electrical and Computer Engineering, Edmonton, AB, Canada, May 9-12, 1999, pp. 427-432.
  58. A. L.-C. Kwong, B. F. Cockburn, and D. G. Elliott, “Dynamic Combined Pattern-Parallel and Fault-Parallel Fault Simulation on Computational RAM,” 1999 IEEE Canadian Conference on Electrical and Computer Engineering, Edmonton, AB, Canada, May 9-12, 1999, pp. 438-445.
  59. M. Redeker, B. F. Cockburn, and D. G. Elliott, “Fault Models and Test Strategies for a Two-bit per Cell DRAM,” 1998 IEEE International Workshop on Memory Technology, Design and Testing, San Jose, CA, U.S.A., Aug. 23-25, 1998, pp. 84-90.
  60. B. F. Cockburn, A. Kwong, and D. G. Elliott, “Parallel Implementations of Transition Fault Simulation on Computational RAM (C*RAM),” 1998 IEEE Canadian Conference on Electrical and Computer Engineering, Waterloo, ON, Canada, May 24-28, 1998, pp. 5-8.
  61. B. F. Cockburn and D. P. Sarda, “Implementation and Evaluation of an Accurate Real-Time Voiceband Signal Classifier,” 1998 IEEE Canadian Conference on Electrical and Computer Engineering, Waterloo, ON, Canada, May 24-28, 1998, pp. 133-136.
  62. B. F. Cockburn and A. L.-C. Kwong, “Transition Maximization Techniques for Enhancing the Two-Pattern Fault Coverage of Pseudorandom Test Pattern Generators,” 1998 IEEE VLSI Test Symposium, Monterey, CA, U.S.A., Apr. 26-30, 1998, pp. 430-437.
  63. B. F. Cockburn, T. Friesen, D. W. K. Tse, “Simplified Jitter Analysis and Performance-enhancing Extensions for the SRTS Mode of ATM AAL-1,” 1997 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, Victoria, BC, Canada, Aug. 20-22, 1997, pp 61-65.
  64. B. F. Cockburn and R. Hang, “A Novel Voiceband QAM Constellation Discrimination Technique,” 1997 IEEE Canadian Conference on Electrical and Computer Engineering, St. John's, NF, Canada, May 25-28, 1997, pp 205-210.
  65. B. F. Cockburn and D. P. Sarda, “A Synthesizable RAM BIST Circuit for Applying an O(n log n) Test that Detects Scrambled Pattern-Sensitive Faults,” 1996 IEEE International Workshop on Memory Technology, Design and Testing, Singapore, Aug. 13-14, 1996, pp. 117-122.
  66. B. F. Cockburn and Y.-F. N. Sat, “Synthesized Transparent BIST for Detecting Scrambled Pattern-Sensitive Faults in RAMs,” 1995 IEEE International Test Conference, Oct. 23-25, 1995, Washington, DC, U.S.A., pp. 23-32.
  67. J. S. Sewall and B.F. Cockburn, “Signal Classification in Digital Telephone Networks,” 1995 IEEE Canadian Conference on Electrical and Computer Engineering, Montreal, PQ, Canada, Sept. 5-8, 1995, pp. 957-961.
  68. B. F. Cockburn, “Deterministic Tests for Detecting Scrambled Pattern-Sensitive Faults in RAMs,” 1995 IEEE International Workshop on Memory Technology, Design and Testing, San Jose, CA, U.S.A., Aug. 7-8, 1995, pp. 117-122.
  69. B. F. Cockburn and N. Y.-F. Sat, “A Transparent Built-In Self-Test Scheme for Detecting Single V-Coupling Faults in RAMs,” 1994 IEEE International Workshop on Memory Technology, Design and Testing, San Jose, CA, U.S.A., Aug. 8-9, 1994, pp. 119-124.
  70. L. Shen and B. F. Cockburn, “A March Test for Fault Type Location in DRAMs,” CCVLSI'93 - 1993 Canadian Conference on Very Large Scale Integration, November 14-16, 1993, Banff, AB, Canada, pp. 4B8-4B14.
  71. B. F. Cockburn, “A 20 MHz Test Vector Generator for Producing Tests that Detect Single 4- and 5-Coupling Faults in RAMs,” 1993 IEEE International Workshop on Memory Testing, San Jose, CA, U.S.A., Aug. 9-10, 1993, pp. 10-14.
  72. L. Shen and B. F. Cockburn, “An Optimal March Test for Locating Faults in DRAMs,” 1993 IEEE International Workshop on Memory Testing, San Jose, CA, U.S.A., Aug. 9-10, 1993, pp. 61-65.

Short Nonrefereed Papers and Poster Papers

  1. Amirhossein Alimohammad, Saeed Fouladi Fard, Bruce F. Cockburn, and Christian Schlegel, “A Flexible Filter Processor for Fading Channel Simulation,” 2007 IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'07), Apr. 23-25, 2007, Napa Valley, CA, USA, 2 pp. abstract and hardware demonstration.
  2. Yufei Yuan, Mrinal K. Mandal and Bruce F. Cockburn, “Embedded Wavelet Image Coder with Parallel Encoding of Bit-planes,” Micronet R&D Annual Workshop, May 10-11, 2005, Ottawa, ON, pp. 85-86.
  3. Gershom Birk, Tyler Brandon, John Koob, Noah Aklilu, Paul Bartosek, Kristopher Breen, Albert Chan, Michael Hume, Craig Joly, Julien Lamoureux, Daniel Leder, Roger Mah, Erica Peter, Ashwin Rao, Michael Redeker, Andrew Sung, Jesus Tapia Hernandez, Sue Ann Ung, Curtis Wickman, Yunan Xiang, Bruce Cockburn and Duncan Elliot, “The Demonstration and Application of Semiconductor File Memories,” Micronet R&D Annual Workshop, May 10-11, 2005, Ottawa, ON, pp. 17-18.
  4. John Koob, Sue Ann Ung, Daniel A. Leder, Craig Joly, Tyler Brandon, Michael Hume, Ashwin Rao, Duncan G. Elliott, and Bruce F. Cockburn, “System-level Evaluation of Semiconductor File Memory,” Micronet R&D Annual Workshop, Apr. 26-27, 2004, Aylmer, QC, 2 pp.
  5. C. Joly, J. Koob, D. Leder, M. Hume, T. Brandon, S.-A. Ung, D. Elliott, and B. Cockburn, “CAM for Yield Enhancement in File Memory,” Micronet R&D Annual Workshop, Sept. 30- Oct. 1, 2003, Toronto, ON, 2 pp.
  6. Y. Xiang, D. Leder, T. Brandon, M. Hume, M. Redeker, and B. Cockburn, “Characterization of a 6-valued Multilevel DRAM,” Micronet R&D Annual Workshop, Apr. 25-26, 2002, Aylmer, QC, pp. 19-20.
  7. R. Sung, J. Koob, T. Brandon, D. Leder, D. Elliott, and B. Cockburn, “3D FD-SOI Memory, Design and Implementation,” Micronet R&D Annual Workshop, Apr. 25-26, 2002, Aylmer, QC, pp. 21-22.
  8. C. Wickman, A. Chan, T. Brandon, Y. Xiang, J. Koob, P. Bartosek, D. Elliott, and B. Cockburn, “Semiconductor File Memory,” Micronet R&D Annual Workshop, Apr. 19-20, 2001, Aylmer, QC, pp. 23-24.
  9. A. Chan, C. Wickman, T. Brandon, D. Elliott, and B. Cockburn, “Semiconductor File Memory,” Micronet R&D Annual Workshop, Apr. 27-28, 2000, Ottawa, ON, pp. 25-26.

Back to Dr. Cockburn's home page

Back to the home page of the Division of Computer Engineering

Back to the home page of the Department of Electrical and Computer Engineering

Back to the home page of the University of Alberta

Last updated October 8, 2009